By Chuan Seng Tan (auth.), Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantsch (eds.)
Back disguise reproduction sequence: built-in Circuits and structures 3D-Integration for NoC-based SoC Architectures through: (Editors) Abbas Sheibanyrad Frédéric Petrot Axel Janstch This e-book investigates at the supplies, demanding situations, and options for the 3D Integration (vertically stacking) of embedded structures attached through a community on a chip. It covers the total architectural layout process for 3D-SoCs. 3D-Integration applied sciences, 3D-Design suggestions, and 3D-Architectures have emerged as subject matters severe for present R&D resulting in a vast variety of goods. This booklet provides a entire, system-level evaluation of 3-dimensional architectures and micro-architectures. •Presents a accomplished, system-level review of three-d architectures and micro-architectures; •Covers the whole architectural layout procedure for 3D-SoCs; •Includes state of the art therapy of 3D-Integration applied sciences, 3D-Design options, and 3D-Architectures.
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Extra resources for 3D Integration for NoC-based SoC Architectures
Garrou, C. Bower, and P. Ramm, Handbook of 3D Integrations: Technology and Applications of 3D Integrated Circuits, Wiley-VCH, Weinheim, ISBN 978-3-527-32034-9, 2008. 24. A. Fan, A. Rahman, and R. Reif, Copper Wafer Bonding. Electrochemical and Solid-State Letters, 2(10), pp. 534–536, 1999. 26 C. S. Tan 25. R. Tadepalli, and Carl V. Thompson, Quantitative Characterization and Process Optimization of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits. Proc. of the IEEE 2003 International Interconnect Technology Conference, pp.
Thus, we get as intrinsic computational efficiency the following. 83 pJ) = 540 GOPS/W The ICE reflects the amount of computation that can be done within an energy envelope, but it does not measure the amount of computations per area or per volume. We now define the Intrinsic Computational Density (â†œICD) as the number of 32-bit adders that fit into 1Â€mm2. 1 shows the intrinsic computational efficiency as a function of technology nodes. 3) for technology nodes between 180 and 17Â€nm are added.
IEEE International Interconnect Technology Conference, pp. 61–63, 2008. 39. T. Osborn, A. He, H. Lightsey, and P. Kohl, All-copper chip-to-substrate interconnects. Proceedings of IEEE Electronic Components and Technology Conference, pp. 67–74, 2008. 40. F. G. F. Ang, J. M. S. Tan, Achieving low temperature Cu to Cu diffusion bonding with self assembly monolayer (SAM) passivation. IEEE International Conference on 3D System Integration, art. no. 5306545, 2009. 41. F. G. F. Ang, J. M. S. Tan, Application of Self Assembly Monolayer (SAM) in Cu–Cu Bonding Enhancement at Low Temperature for 3-D Integration, Advanced Metallization Conference, Baltimore, October 13–15, 2009.